1. Technical Field
The present disclosure relates to a patterning process of semiconductor manufacturing, in particular, to a method for compensating the effect of a patterning process and an apparatus thereof, wherein the method for compensating the effect of the patterning process is a non-delta-chrome optical proximity correction (non-DCOPC) method in the patterning process of semiconductor manufacturing, and the patterning process represents a lithography process or an etching process.
2. Description of Related Art
Patterning is an important process in the semiconductor manufacturing. By using the patterning process, the semiconductor manufacturers optimize the layout on a photomask which is based on the drawn layout from the integrated circuit (IC) designers, and then use a light source projects the layout on the photomask to the wafer, thus forming the actual layout on the wafer. Without any patterning process effect, the actual layout on the wafer is ideally identical to the layout on the photomask.
Generally speaking, the minimum line width of the lithography is proportional to the wavelength of the light source. In other words, the less the line width is, the shorter the wavelength of the light source is adapted in the patterning process.
Referring to FIG. 1A, FIG. 1A is schematic diagram showing the actual layout on the wafer in the case that the layout of the photomask is not corrected by the optical proximity correction (OPC) method. After the light source passes the photomask, the actual layout 13 is formed on the wafer. Without any patterning process effect, the drawn layout 12 (also called desired layout) on the wafer is identical to the layout 11 on the photomask. However, due to the diffraction, the actual layout 13 on the wafer is not the same as layout 11 on the photomask.
To make the actual layout 13 on the wafer close to the drawn layout 12 on the wafer, an OPC method is proposed to correct the layout 11 on the photomask. Referring to FIG. 1B, FIG. 1B is a schematic diagram showing the actual layout on the wafer in the case that the layout on the photomask is corrected by the OPC method. The OPC method corrects the patterning process effect to generate the layout 11 on the photomask. After the light source passes the layout 11 on the photomask, the actual layout 13 is formed on the wafer, wherein the actual layout 13 is close to the drawn layout 12 on the wafer.
Since the IC design dimensions shrink to the deep sub-wavelength regime, some nonlinear patterning process effect, such as mask topographic effect, resist development effect, and etching proximity effect ignored by the conventional OPC method have become significant for accurate OPC. Currently, the delta-chrome OPC (DCOPC) method with the OPC process model has to take into account the previously ignored nonlinear patterning process effect.
The DCOPC method runs a dense simulation for calculating the edge placement error (EPE) values of all segments. If the EPE values are not satisfied, the computation of the mask perturbation response to predict the amount of the proper chrome change is performed using a sparse simulation on a segment-by-segment basis. The step for adjusting the chrome change of each segment is iteratively performed until the EPE value is satisfied. The total run time is proportional to the number of the iterations required. Accordingly, the DCOPC method is challenged owing to the large complexity of the computation of the mask perturbation response.